1.Comparing Design Hierarchies 比較golden 與 revised verilog
 
The WRITE HIER_COMPARE DOFILE command lets you write a dofile script that Conformal can use to compare two hierarchical designs. The dofile script verifies the two hierarchical designs starting at the lowest-level modules and progressing to the root module. At the end of the dofile, Conformal displays the total number of equivalent and non-equivalent modules.

The sample dofile below does the following:
-Reads in the two hierarchical designs
-Writes out the hierarchical dofile script
-Compares the design hierarchy
 
指令如下

2.Comparing Libraries 比較 standard cell .lib 與 verilog
 
In addition to comparing design hierarchies, the WRITE HIER_COMPARE DOFILE command compares two libraries, such as Liberty and Verilog libraries. The sample dofile below does the following:
-Reads in a synthesis library and simulation library
-Writes out all of the library models
-Compares the libraries

指令如下

3. 檢查 netlist

4.自動化script
 
把要跑的指令寫到 lec.script
然後在terminal 執行

ERIC7423

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